1. Technical Field
Embodiments generally relate to memory architectures. In particular, embodiments relate to the selective buffering of memory data signals.
2. Discussion
Memory architectures can be an important aspect of computing systems. In particular, the DDR3 (e.g., Double Data Rate Three Specification, JEDEC Solid State Technology Association, JESD79-3C, November 2008), synchronous dynamic random access memory (SDRAM) interface architecture may have facilitated higher bandwidth storage of the working data of a wide variety of computing systems in recent years. DDR3 SDRAM may often be configured as dual inline memory modules (DIMMs). The most common type of memory module may be un-buffered DIMM (UDIMM) in which all of the DRAM ranks (e.g., chips) are a load on the memory bus. While such a scheme may provide the lowest cost, memory access speed can suffer when higher capacity (e.g., more than 1 DIMM per channel) is needed. Another type of memory module may be the registered DIMM (RDIMM), which can improve access performance by buffering the command and address bus signals on the DIMM. This approach may use a data multiplexer (e.g., DQ-MUX), however, to switch between DIMMs, wherein the DQ-MUX can have a large amount of input/output (e.g., JO) pins when there are multiple DIMMs. In addition, the DQ-MUX may reside on the motherboard, which could unnecessarily increase the cost of the motherboard in instances where multiple DIMMs might not be deployed. Load-Reduced DIMMs (LRDIMMs) can extend buffering to include the data bus and data strobes and improve the signal integrity, but at a potential cost of the extra power that the LRDIMM buffer may consume (e.g., 3× more than the RDIMM buffer).